View DS12885S_271080.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS12885, DS12885Q, DS12885T Real Time Clock
www.dalsemi.com
FEATURES
Drop-in replacement for IBM AT computer clock/calendar Pin configuration closely matches MC146818B and DS1285 Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year compensation valid up to 2100 Binary or BCD representation of time, calendar, and alarm 12- or 24-hour clock with AM and PM in 12-hour mode Daylight Savings Time option Selectable between Motorola and Intel bus timing Multiplex bus for pin efficiency Interfaced with software as 128 RAM locations 14 bytes of clock and control registers 114 bytes of general purpose RAM Programmable square wave output signal Bus compatible interrupt signals ( IRQ ) Three interrupts are separately software- maskable and testable Time-of-day alarm once/second to once/day Periodic rates from 122 s to 500 ms End of clock update cycle Optional 28-pin PLCC surface mount package or 32-pin TQFP Optional industrial temperature range available
PIN ASSIGNMENT
1 of 6
062000
DS12885, DS12885Q, DS12885T
DESCRIPTION
The DS12885 Real Time Clock plus RAM is designed to be a direct replacement for the DS1285. The DS12885 is identical in form, fit, and function to the DS1285, and has an additional 64 bytes of general purpose RAM. Access to this additional RAM space is determined by the logic level presented on AD6 during the address portion of an access cycle. An external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power. For a complete description of operating conditions, electrical characteristics, bus timing, and pin descriptions other than X1, X2, VBAT, and RCLR , see the DS12887 data sheet.
PIN DESCRIPTION
AD0-AD7 NC MOT
CS
AS R/ W DS
RESET
- Multiplexed Address/Data Bus - No Connection - Bus Type Selection - Chip Select - Address Strobe - Read/Write Input - Data Strobe - Reset Input
IRQ
SQW VCC GND X1,X2 VBAT
RCLR
- Interrupt Request Output (open drain) - Square Wave Output - +5V Supply - Ground - 32.768 kHz Crystal Connections - +3V Battery Input - RAM Clear
PIN DESCRIPTION
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal area. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, "Crystal Considerations with Dallas Real Time Clocks." VBAT - Battery input for any standard 3-volt lithium cell or other energy source. Battery voltage must be held between 2.5 and 4 volts for proper operation. A maximum load of 0.5 A at 25C in the absence of power should be used to size the external energy source. The battery should be connected directly to the VBAT pin. A diode must not be placed in series with the battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current protection circuitry is provided internal to the device and has passed the requirements of Underwriters Laboratories for UL listing.
RCLR - The RCLR pin is used to clear (set to logic 1) all 114 bytes of general purpose RAM but does
not affect the RAM associated with the real time clock. In order to clear the RAM, RCLR must be forced to an input logic "0" (-0.3 to +0.8 volts) during battery back-up mode when VCC is not applied. The RCLR function is designed to be used via human interface (shorting to ground manually or by switch) and not to be driven with external buffers. This pin is internally pulled up. Do not use an external pull- up resistor on this pin.
2 of 6
DS12885, DS12885Q, DS12885T
DS12885 24-PIN DIP
PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 24-PIN MIN MAX 1.245 1.270 31.62 32.25 0.530 0.550 13.46 13.97 0.145 0.165 3.68 4.19 0.600 0.625 15.24 15.88 0.015 0.050 0.380 1.27 0.120 0.145 3.05 3.68 0.090 0.110 2.29 2.79 0.625 0.675 15.88 17.15 0.008 0.012 0.20 0.30 0.015 0.022 0.38 0.559
3 of 6
DS12885, DS12885Q, DS12885T
DS12885 24-PIN SOIC
LTR IN. A MM IN A1 MM IN A2 MM IN B MM IN C MM IN D MM IN E MM IN E1 MM IN H MM IN L MM
MIN 0.094 2.39 0.004 0.102 0.089 2.26 0.013 0.33 0.009 0.229 0.598 15.19 .050 1.27 0.290 7.37 0.398 10.11 0.016 0.40 0
MAX 0.105 2.67 0.012 0.30 0.095 2.41 0.020 0.51 0.013 0.33 0.612 15.54 BSC BSC 0.300 7.62 0.416 10.57 0.040 1.02 8
The chamfer on the body is optional. If it is not present, a terminal 1 identifier must be positioned so that 1/2 or more of it's area is contained in the hatched zone.
4 of 6
DS12885, DS12885Q, DS12885T
DS12885Q 28-PIN PLCC
LTR A A1 A2 B B1 C D D1 D2 E E1 E2 L1 N E1 CH1
MIN MAX .165 .180 .090 .120 .020 0.26 .033 .013 .021 .009 .012 .485 .495 .450 .456 .390 .430 .485 .495 .450 .456 .390 .430 .060 28 .050 BSC .042 .048
5 of 6
DS12885, DS12885Q, DS12885T
DS12885T 32-PIN TQFP
6 of 6

▲Up To Search▲

Price & Availability of DS12885S

	To Download DS12885S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .